Michigan State University - Research Groups

This paper presents the implementation of a low-power and implantable neuroprocessor on low-cost nano-FPGA for data reduction and on-the-fly spike sorting in Brain Machine Interface applications. Detailed analysis of efficient utilization of the hardware resources, power consumption and design scalability are provided. The prototype we report here enables simultaneous processing of 32-channel data sampled at 25 kHz/channel with 8-
bit/sample resolution with less than 5 mW power consumption for all modes of operation (monitoring, compression and sensing) at 1.2 V core voltage supply on a 5 mm × 5 mm nano-FPGA.